The present invention relates to the field of semiconductors, in particular to a neuron device and a method of making the same.
With the development of integrated circuits and the improvements in the degree of integration, there have been many difficulties and unsolved problems with conventional silicon integrated circuits based on single transistor functionality. For example, the ability to further increase the density of components on a chip is limited. Neuron MOS transistors (Neuron Metal-Oxide Semiconductor Field Effect Transistor, abbreviated as neuMOS or vMOS) as powerful single-cell transistors provide an effective way of addressing the increasing number of transistors in integrated circuits and interconnection lines.
A neuron MOS transistor has a floating gate, which is capacitively coupled to the input terminal. The functionalities of a neuron device are similar to those of the nerve cells forming the human brain, the eye, and the like. Specifically, a neuron device provides a weighted sum of a plurality of input signals and outputs a predetermined signal when the resultant weighted sum of input signals reaches a predetermined threshold value. Such a neuron device includes a weighting tool for providing a weighted sum of a plurality of input signals. When the weighted sum of input voltages reaches a predetermined value, the source and the drain of the neuron device become conducting with respect to each other. The weighting tool is equivalent to a synapse between neuron cells. For example, the weighting tool may include resistors and field effect transistors. A neuron transistor is equivalent to the cell body of a neuron cell.
FIG. 12A shows a schematic diagram of a neuron MOS transistor. FIG. 12B shows an equivalent circuit diagram of a neuron MOS transistor with a floating gate and a plurality of input gates. FIG. 12C shows a simplified schematic diagram of a neuron MOS transistor. As shown in FIG. 12A, the neuron MOS transistor includes a substrate 1205, a source 1201, a drain 1202, a floating gate 1203, and a plurality of input gates 1204. As shown in FIG. 12B, each input electrode forms a respective equivalent capacitor with the floating gate, having a respective capacitance of C1, C2, C3, . . . Cn, respectively. The two plates of each respective capacitor have a charge of Q1, Q2, Q3, . . . Qn, respectively. The floating gate and the substrate form an equivalent capacitor having a capacitance of C0, and a charge of Q0. Assuming there is no charge injection during device operation, the charge on the floating gate is the initial charge. In order to simplify, it is assumed that the initial charge is zero. Assuming that the substrate is grounded, by calculating the weighted sum of the input signals at the plurality of input electrodes, the electric potential of the floating gate is:
      Φ    F    =                    ∑                  i          =          1                k            ⁢                          ⁢                        C          i                ⁢                  V          i                                              ∑                      i            =            1                    k                ⁢                                  ⁢                  C          i                    +              C        0            wherein, ΦF is the floating gate potential, and Vi is the voltage on each capacitor. When the floating gate potential ΦF is greater than the threshold voltage Vth, the source 1201 and the drain 1203 is turned on.
Such a neuron MOS transistor has many uses. It can be used as an inverter. For example, one may connect the source electrode (or the drain electrode) of the neuron MOS transistor to a power source VDD via a resistor, connect the drain electrode (or the source electrode) to the ground, and use the plurality of input gates as input. When the floating gate potential ΦF is greater than the threshold voltage Vth, the inverter outputs a logic “0”; and when ΦF is greater than Vth, the inverter outputs a logic “1.”